High-speed parallel decision feedback equalizer

ABSTRACT

A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules. One illustrative embodiment includes a front end filter to reduce leading intersymbol interference in a receive signal; a serial-to-parallel converter and at least one pre-compensation unit that together convert the filtered signal into grouped sets of tentative decisions, the sets in each group being made available in parallel; a set of pipelined DFE multiplexer units to select a contingent symbol decision from each set of tentative decisions to form groups of contingent symbol decisions based on a presumed sequence of preceding symbol decisions; and an output multiplexer that chooses, based on preceding symbol decisions, one of said groups of contingent symbol decisions.

BACKGROUND

Digital communications occur between sending and receiving devices overan intermediate communications medium, or “channel” (e.g., a fiber opticcable or insulated copper wires). Each sending device typicallytransmits symbols at a fixed symbol rate, while each receiving devicedetects a (potentially corrupted) sequence of symbols and attempts toreconstruct the transmitted data. A “symbol” is a state or significantcondition of the channel that persists for a fixed period of time,called a “symbol interval.” A symbol may be, for example, an electricalvoltage or current level, an optical power level, a phase value, or aparticular frequency or wavelength. A change from one channel state toanother is called a symbol transition. Each symbol may represent (i.e.,encode) one or more binary bits of the data. Alternatively, the data maybe represented by symbol transitions, or by a sequence of two or moresymbols.

The simplest digital communication links use only one bit per symbol; abinary ‘0’ is represented by one symbol (e.g., an electrical voltage orcurrent signal within a first range), and binary ‘1’ by another symbol(e.g., an electrical voltage or current signal within a second range).Channel non-idealities produce dispersion which may cause each symbol toperturb its neighboring symbols, causing intersymbol interference (ISI).ISI can make it difficult for the receiving device to determine whichsymbols were sent in each interval, particularly when such ISI iscombined with additive noise.

To combat noise and ISI, receiving devices may employ variousequalization techniques. Linear equalizers generally have to balancebetween reducing ISI and avoiding noise amplification. Decision FeedbackEqualizers (DFE) are often preferred for their ability to combat ISIwithout inherently requiring noise amplification. As the name suggests,a DFE employs a feedback path to remove ISI effects derived frompreviously-decided symbols.

A standard textbook implementation of a DFE employs a number of cascadedcircuit elements to generate the feedback signal and apply it to thereceived input signal, all of which must complete their operation inless than one symbol interval. At a symbol interval of 100 picoseconds(for a symbol rate of 10 Gbit/s), this implementation is infeasible withcurrently available silicon semiconductor processing technologies. Evendata rates around a few gigabits per second can be difficult to achievedue to performance limitations of silicon-based integrated circuits.

SUMMARY

Accordingly, there are disclosed herein apparatus and methods employingparallelization and pre-computation techniques to implement decisionfeedback equalization (DFE) at bit rates above 10 Gbit/s, making itfeasible to employ DFE in silicon-based optical transceiver modules. Oneillustrative embodiment includes a front end filter to reduce leadingintersymbol interference in a receive signal; a serial-to-parallelconverter and at least one pre-compensation unit that together convertthe filtered signal into grouped sets of tentative decisions, the setsin each group being made available in parallel; a set of pipelined DFEmultiplexer units to select a contingent symbol decision from each setof tentative decisions to form groups of contingent symbol decisionsbased on a presumed sequence of preceding symbol decisions; and anoutput multiplexer that chooses, based on preceding symbol decisions,one of said groups of contingent symbol decisions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an illustrative computer network.

FIG. 2 is a function-block diagram of an illustrative point-to-pointcommunication link.

FIG. 3 is a function-block diagram of an illustrative fiber opticinterface module.

FIG. 4 shows an illustrative textbook decision feedback equalizer (DFE)implementation.

FIG. 5 shows an illustrative DFE employing a one-tap pre-computationunit.

FIG. 6 shows an illustrative DFE with a fully-unrolled pre-computationunit.

FIG. 7A shows an illustrative DFE front end that produces a parallelarray of pre-computed signal sets.

FIG. 7B shows an illustrative pipelined DFE multiplexer unit.

FIG. 7C shows a condensed representation of a pipelined DFE multiplexerunit.

FIG. 7D shows an illustrative DFE back end having a parallel array ofpipelined DFE multiplexer units.

FIG. 8 is a flowchart of an illustrative equalization method for highspeed receiving devices.

It should be understood, however, that the specific embodiments given inthe drawings and detailed description do not limit the disclosure. Onthe contrary, they provide the foundation for one of ordinary skill todiscern the alternative forms, equivalents, and modifications that areencompassed in the scope of the appended claims.

DETAILED DESCRIPTION

The disclosed apparatus and methods are best understood in the contextof the larger environments in which they operate. Accordingly, FIG. 1shows an illustrative communications network 100 including mobiledevices 102 and computer systems 104A-C coupled via a routing network106. The routing network 106 may be or include, for example, theInternet, a wide area network, or a local area network. In FIG. 1, therouting network 106 includes a network of equipment items 108, such asswitches, routers, and the like. The equipment items 108 are connectedto one another, and to the computer systems 104A-C, via point-to-pointcommunication links 110 that transport data between the various networkcomponents.

FIG. 2 is a diagram of an illustrative point-to-point communication linkthat may be representative of links 110 in FIG. 1. The illustratedembodiment includes a first node 202 (“Node A”) in communication with asecond node 204 (“Node B”). Nodes A & B can each be, for example, anyone of mobile devices 102, equipment items 108, computer systems 104A-C,or other sending/receiving devices suitable for high-rate digital datacommunications.

Coupled to Node A is a transceiver 220, and coupled to Node B is atransceiver 222. Communication channels 208 and 214 extend between thetransceivers 220 and 222. The channels 208 and 214 may include, forexample, transmission media such as fiber optic cables, twisted pairwires, coaxial cables, backplane transmission lines, and wirelesscommunication links. (It is also possible for the channel to be amagnetic or optical information storage medium, with the write-readtransducers serving as transmitters and receivers.) Bidirectionalcommunication between Node A and Node B can be provided using separatechannels 208 and 214, or in some embodiments, a single channel thattransports signals in opposing directions without interference.

A transmitter 206 of the transceiver 220 receives data from Node A andtransmits the data to the transceiver 222 via a signal on the channel208. The signal may be, for example, an electrical voltage, anelectrical current, an optical power level, a wavelength, a frequency,or a phase value. A receiver 210 of the transceiver 222 receives thesignal via the channel 208, uses the signal to reconstruct thetransmitted data, and provides the data to Node B. Similarly, atransmitter 212 of the transceiver 222 receives data from Node B, andtransmits the data to the transceiver 220 via a signal on the channel214. A receiver 216 of the transceiver 220 receives the signal via thechannel 214, uses the signal to reconstruct the transmitted data, andprovides the data to Node A.

FIG. 3 illustrates a transceiver embodiment specific to fiber opticsignaling with a function block diagram of an illustrative fiber opticinterface module. The optical fiber 302 couples to a splitter 304 whichcreates two optical paths to the fiber: one for receiving and one fortransmitting. A sensor 306 is positioned on the receiving path toconvert received optical signals into analog electrical signals that areamplified by amplifier 308 in preparation for processing by a decisionfeedback equalizer (DFE) 310. The DFE 310 reconstructs a digital datastream from the received signal. A device interface 312 buffers thereceived data stream and, in some embodiments, performs error correctionand payload extraction to make the transmitted data available to thehost node via an internal data bus in accordance with a standard I/O busprotocol.

Conversely, data for transmission can be communicated by the host nodevia the bus to device interface 312. In at least some embodiments, thedevice interface 312 packetizes the data with appropriate headers andend-of-frame markers, optionally adding a layer of error correctioncoding and/or a checksum. Driver 314 accepts a transmit data stream frominterface 312 and converts the digital signals into an analog electricaldrive signal for emitter 316, causing the emitter to generate opticalsignals that are coupled via splitter 304 to the optical fiber 302.

As previously mentioned, a DFE is included in the receive chain tocombat intersymbol interference (ISI) that results from signaldispersion in the channel. FIG. 4 shows an illustrative “textbook”implementation of a DFE. In FIG. 4, an analog or digital front endfilter 402 operates on the receive signal to shape the overall channelresponse of the system and minimize the effects of leading ISI on thecurrent symbol. A summer 404 subtracts a feedback signal from the outputof the front end filter 402 to minimize the effects of trailing ISI onthe current symbol. The combined signal is then digitized to produce astream of output data (denoted A_(k), where k is the time index). In theillustrated example, the symbols are presumed to be bipolar (−1, +1),making the decision threshold 0 volts. A quantizer 408 produces a binaryresult: 0 if the output of summer 404 is below the threshold and 1 ifthe output is above the threshold. The DFE generates the feedback signalwith a feedback filter 410 having a series of delay elements 412 (e.g.,latches, flip flops, or registers) that store the recent output symboldecisions (A_(k−1) . . . A_(k−N), where N is the number of filtercoefficients f_(i)). A series of multipliers 414 determines the productof each symbol with a corresponding filter coefficient, and a series ofsummers 416 combines the products to obtain the feedback signal.

As an aside, we note here that the circuitry for the front end filter402 and the feedback filter 410 can operate on analog signals, orconversely, it can be implemented using digital circuit elements and/orsoftware in a programmable processor. Further, the DFE can be readilyextended from detecting binary symbols to M-ary symbols with the use ofadditional decision thresholds. Typically, a timing recovery unit and afilter coefficient adaptation unit augment the operation of the DFE, butsuch considerations are addressed in the literature and known to thoseskilled in the art, so we will not dwell on them here.

In the embodiment of FIG. 4, the feedback filter 410 must complete itsoperation in less than one symbol interval because its current outputdepends in part upon the immediately preceding decision. At very highdata rates, one symbol interval does not provide sufficient time tofinish the filter multiplications and the feedback subtraction.Accordingly, one solution that has been proposed in the literature is“unrolling” the feedback filter. FIG. 5 shows an illustrative variationof FIG. 4 that unrolls the feedback filter by one tap. The embodiment ofFIG. 5 employs the same front end filter 402, but summer 404 subtracts afeedback signal to remove the trailing ISI caused by all but theimmediately preceding symbol. A pre-compensation unit 406 provides twopaths. A quantizer 407 on the first path forms a tentative symboldecision assuming that the immediately preceding symbol was a “1”, whilea second quantizer 409 on the second path forms a tentative symboldecision assuming that the immediately preceding symbol was a “0”(corresponding to a −1 in a bipolar signaling scheme). As the trailingISI from these symbols is different (+f₁ for a +1 symbol, and for a −1symbol), the two paths provide different compensation for the ISI,either by using different decision thresholds as indicated in FIG. 5, orby biasing the signal paths by different amounts. A multiplexer 413selects between the two tentative decisions based on the immediatelypreceding symbol decision A_(k−1), which is stored by flip flop 415.Feedback filter 419 has a reduced number of taps (filter coefficients),but otherwise operates similarly to feedback filter 410.

Although this unrolling step increases the number of elements in the DFEloop (summer 404, precompensation unit 406, multiplexer 413, andfeedback filter 419), only the multiplexer 413 and flip flop 415) needto achieve their operations in less than one symbol interval. Theremaining loop elements can take up to two symbol intervals to operate.If it is still a challenge to complete the feedback filter operation intime, further unrolling can be performed.

FIG. 6 shows an illustrative variation in which a 3-tap feedback filterhas been completely unrolled. This embodiment still employs front endfilter 402, but the summer is eliminated since the feedback filter hasbeen completely unrolled. Its function has been fully supplanted byprecompensation unit 606, which provides a separate path for eachcombination of the three preceding symbols, e.g., 000, 001, 010, . . . ,111. The trailing ISI from each of these possible combinations isdetermined and removed (e.g., with a summer) or otherwise compensatedfor (e.g., using suitable decision thresholds for the quantizers on eachpath). Each path has a respective quantizer 607-609 that provides atentative symbol decision subject to the presumed combination ofpreceding symbols. The set of eight tentative decisions is labeled inFIG. 6 as B0_(k)-B7_(k), where k is again the time index. A multiplexer613 selects from the set of tentative symbol decisions based on thepreceding symbol decisions held in flip flops 615-617, producing thesequence of symbol decisions A_(k).

Notably, such unrolling can address timing constraints on the feedbackfilter, but the operating time by flip flop 615 and multiplexer 613 maybecome the limiting factor at very high data rates. In other words, forany given semiconductor process, the propagation delay of themultiplexer becomes a bottleneck to the loop-unrolling approach as thedata rate increases. FIGS. 7A-7D illustrate a novel DFE embodiment thatemploys a unique parallel architecture that can essentially be scaled asneeded to fundamentally eliminate this feedback loop timing as alimiting factor on the data rate.

FIG. 7A shows an illustrative DFE front end that produces a parallelarray of pre-computed signal sets. FIG. 7A shows a front end filter 402that, as before, shapes the overall channel response of the system andminimizes leading ISI. A precompensation unit 606 (for fully unrollingthe feedback filter) derives a full set of tentative decisionsB0_(k)-B(2^(N)−1)_(k) for each symbol interval k (assuming binarysymbols), where N is the number of the number of previous symbolscausing trailing ISI. (FIG. 6 provides an example of a precompensationunit for a 3-symbol trailing ISI effect, but in practice the number ofsymbols may be larger or smaller.)

A serial to parallel converter 702 accepts the sequence of tentativedecision sets and provides them in parallel as groups of P sets. (In thefigures, open face lettering is used to represent a group of P signals,e.g.,

0(L) represents the group of signals B0_(LP)-B0_(LP+P−1).) A set ofregisters 703 may latch in a round-robin fashion to capture eachtentative decision set as it becomes available and to hold it for aslong as necessary for subsequent processing, i.e., up to P symbolintervals. Other implementations of serial-to-parallel conversion unitsare known and can be used. Some implementations provide the captured setof tentative decisions as output upon capture, whereas others may storethe captured sets to be output simultaneously as a whole group. Theoutput of the serial to parallel converter corresponds to the input inFIGS. 7B-7D.

FIG. 7B shows an illustrative pipelined DFE multiplexer unit 704. Unit704 selects one signal from each set of tentative decisions as a symboldecision, thereby producing P symbol decisions from P sets of tentativedecisions. For each set of tentative decisions B0_(k)-B(2^(N) ⁻¹)_(k),unit 704 employs a respective multiplexer 710, 712, . . . , 716 toforward a selected decision from each set. Where symbol decisions areavailable for the N preceding symbol intervals, the multiplexers maketheir selections based on those symbol decisions. For the beginning ofeach group, the N preceding symbol decisions are taken as inputs to theunit (denoted in the figure as A_(LP−1) to A_(LP−N) N). These inputs areshown in FIG. 7A as estimates for reasons explained further below.

A group of flip flops 720-726 latch the P symbol decisions and providethem as a group C_(LP−P)-C_(LP−1) (also represented as

(L−1)). Due to the serial-to-parallel operation, each of the elements ofunit 704 has up to P symbol intervals to perform each operation. FIG. 7Balso shows an optional group of input delay elements 732-736 and anoptional group of output delay elements 740-744. Such optional delayelements may be desirable to provide a consistent propagation delayalong each of the P parallel paths through the unit 704 while alsoaccounting for the delays required for the multiplexer outputs tocascade across the unit. Accordingly, the optional delay elements areshown incrementing or decrementing by d, the delay associated with theoperation of each multiplexer.

FIG. 7C shows a condensed representation of a pipelined DFE multiplexerunit of FIG. 7B. As previously explained, the unit 704 makes a selectionfrom each set of tentative decisions based on the preceding symboldecisions, thereby producing a group of symbol decisions, hereafterreferred to as contingent symbol decisions for reasons that will becomeclear in the discussion of FIG. 7D.

FIG. 7D shows an illustrative DFE back end having a parallel array of2^(N) pipelined DFE multiplexer units 704A-704C. The group of tentativedecision sets from the DFE front end in FIG. 7A is distributed to all ofthe pipelined DFE multiplexer units for processing by each unit. Eachunit operates on the group of tentative decision sets to provide arespective group of contingent symbol decisions (labeled in FIG. 7D as

0(L−1)-

(2^(N)−1)(L−1)). Each pipelined DFE multiplexer unit presumes adifferent sequence of preceding symbol decisions. For example, unit 704Apresumes that the preceding N symbol decisions are all zero, unit 704Bpresumes that the preceding N−1 symbol decisions are zero and the Nthpreceding symbol decision is one, and so on through unit 704C whichpresumes the preceding symbol decisions are all ones.

Because the initial presumption is different for each unit, the group ofcontingent symbol decisions

n(L−1) should be expected to vary between units. A multiplexer 753selects one group of contingent symbol decisions based on the N (actual)preceding symbol decisions A(L−2) stored in a latch 755. In FIG. 7D, theselected group of symbol decisions (labeled

(L−1)), is latched by latch 755, which holds the group of P symbols forup to P symbol intervals.

If the multiplexing operations employ 2-to-1 selectors, only N stagesare needed for the multiplexing operations, meaning that the delayassociated with multiplexer 753 is linear in N. (We focus on multiplexer753 because this is the only portion of the circuit having a feedbackloop. Everything else is implemented as a (possibly pipelined) feedforward arrangement.) This total mux delay must be kept smaller than thetime interval PT, where P is the parallelization factor and T is thesymbol interval. Since the parallelization factor P can be made as largeas desired, the circuit designer is not prevented by an irreduciblefeedback loop delay from providing a circuit capable of handling anarbitrarily small symbol interval with arbitrarily slow devices (gates).Contrast this with the unrolled-loop DFE architecture where the muxdelay must be safely smaller than the symbol interval, creating aninsurmountable data rate limit for a given device (gate) speed.

FIG. 8 is a flowchart of an illustrative DFE-based equalization methodfor use by high speed receiving devices. For explanatory purposes, theoperations are shown and described in sequential order, but it isexpected that the operations would typically be performed concurrentlyby different portions of the device. Nevertheless, a sequentialimplementation is possible and in some implementations may be preferred(e.g., by software on a programmable processor).

In block 802, the DFE filters the incoming signal with, e.g., a frontend filter that shapes the overall channel response and minimizesleading ISI. In block 804, the DFE precompensates for trailing ISI,using multiple paths corresponding to the various amounts of trailingISI from the different possible preceding symbol decisions. A tentativesymbol decision is made on each path, yielding a set of 2^(N) tentativedecisions. In block 806, the DFE takes P sequential sets of tentativedecisions and provides them in parallel as a group. In block 808, thegroup of sets is distributed to each of 2 ^(N) pipelined DFE multiplexerunits. Each of the DFE multiplexer units selects a tentative decisionfrom each set, yielding a group of decision symbols contingent upon apresumed sequence of preceding decision symbols. The presumed sequenceis different for each pipelined DFE multiplexer unit. In block 810, theDFE selects one group of contingent decision symbols based upon theactual sequence of preceding decision symbols. In block 812, theselected group is latched and output as a group of actual decisionsymbols.

Numerous alternative forms, equivalents, and modifications will becomeapparent to those skilled in the art once the above disclosure is fullyappreciated. For example, the various DFE components can be implementedwith analog electrical components or with digital electrical components.In many cases, the order of elements can be changed, e.g., performingthe precompensation after the serial-to-parallel conversion, though thisnecessitates multiple precompensation units operating in parallel. Thenumber of trailing ISI symbol intervals N can be 1, 2, 3, 4, or more.The parallelization factor P can be 2, 3, 4, 5, or more. The number ofpermissible symbol decisions may be binary or M-ary where M is usually apower of 2. It is intended that the claims be interpreted to embrace allsuch alternative forms, equivalents, and modifications that areencompassed in the scope of the appended claims.

What is claimed is:
 1. A high speed equalization method that comprises:deriving at each of multiple consecutive time intervals a set oftentative decisions, each tentative decision accounting for a respectivedegree of trailing intersymbol interference from an assumed sequence ofpreceding symbol decisions; forming a parallel group from a series ofsaid sets of tentative decisions; applying the parallel group to a setof pipelined DFE multiplexer units, each said unit selecting acontingent symbol decision from each set of tentative decisions in thegroup to form a group of contingent symbol decisions based on a presumedsequence of preceding symbol decisions; and choosing, based on an actualsequence of preceding symbol decisions, one of said groups of contingentsymbol decisions as a group of actual symbol decisions.
 2. The method ofclaim 1, wherein said deriving includes: minimizing leading intersymbolinterference with a front end filter, thereby providing a filtered inputsignal; and distributing the filtered input signal across a set ofpaths, each path compensating the filtered input signal for a respectivedegree of trailing intersymbol interference.
 3. The method of claim 1,wherein the set of tentative decisions and the set of pipelined DFEmultiplexer units each have a cardinality of 2^(N), where N is a numberof preceding symbols causing trailing intersymbol interference.
 4. Themethod of claim 1, wherein each group has a cardinality of P, wherein Pis an integer parallelization factor at least equal to
 2. 5. The methodof claim 1, further comprising latching the group of actual symboldecisions.
 6. The method of claim 1, further comprising applying N mostrecent actual symbol decisions to a multiplexer that performs saidchoosing.
 7. A high speed equalizer that comprises: a front end filterthat reduces leading intersymbol interference in a receive signal toprovide a filtered signal; a serial-to-parallel converter and at leastone precompensation unit that together convert the filtered signal intogrouped sets of tentative decisions, the sets in each group being madeavailable in parallel; a set of pipelined DFE multiplexer units, eachmultiplexer unit selecting a contingent symbol decision from each set oftentative decisions in each group to form groups of contingent symboldecisions based on a presumed sequence of preceding symbol decisions;and an output multiplexer that chooses, based on an actual sequence ofpreceding symbol decisions, one of said groups of contingent symboldecisions as a group of actual symbol decisions.
 8. The equalizer ofclaim 7, further comprising an output latch that holds the actual symboldecisions for group interval delay.
 9. The equalizer of claim 7, whereinthe precompensation unit derives digital decisions from analog signals.10. The equalizer of claim 9, wherein the precompensation unit outputsdecisions at a rate in excess of 10 GHz.
 11. The equalizer of claim 7,wherein the front end filter, serial-to-parallel converter, andprecompensation unit are implemented with digital circuit elements. 12.The equalizer of claim 7, wherein the set of tentative decisions and theset of pipelined DFE multiplexer units each have a cardinality of 2^(N),where N is a number of preceding symbols causing trailing intersymbolinterference, and wherein each group has a cardinality of P, wherein Pis an integer parallelization factor at least equal to
 2. 13. A channelinterface module that comprises a receiver having: a sensor thatconverts receive channel signals into electrical signals; a front endfilter that enhances the signal-to-noise ratio of the electricalsignals; at least one precompensation unit and a serial-to-parallelconverter that together produce groups of tentative decision sets, thesets in each group being made available in parallel; a set ofmultiplexer units that each operate on each group to obtain a group ofcontingent decisions based on a presumed sequence of preceding symboldecisions; an output multiplexer that, based on actual preceding symboldecisions, chooses groups of actual symbol decisions from the groups ofcontingent decisions; and a device interface that provides a host nodewith a received data stream derived from the groups of actual symboldecisions.
 14. The module of claim 13, further comprising a transmitterthat receives a transmit data stream from said device interface andconverts said transmit data stream to a transmit channel signal.
 15. Themodule of claim 14, wherein the received data stream carries at least 10Gbit/s.
 16. The module of claim 13, wherein the receiver furtherincludes an output latch that holds the groups of actual symboldecisions for group interval delay.
 17. The module of claim 13, whereinthe tentative decision sets and the set of multiplexer units each have acardinality of 2^(N), where N is a number of preceding symbols causingtrailing intersymbol interference.
 18. The module of claim 13, whereinthe output multiplexer employs N most recent actual symbol decisionsfrom a preceding group of actual symbol decisions to perform saidchoosing.
 19. The module of claim 17, wherein each group has acardinality of P, wherein P is an integer parallelization factor atleast equal to
 2. 20. The module of claim 19, wherein P is greater thanN.
 21. The module of claim 13, wherein the transmit and receive channelsignals are optical signals.
 22. The module of claim 13, wherein thechannel is an information storage medium.
 23. The module of claim 13,wherein the transmit and receive channel signals are electromagneticsignals conveyed via twisted wire pair, coaxial cable, or backplanetransmission lines.